Traffic and Power Reduction Routing Algorithm for Noc Cores

With the progress of VLSI technology, the number of cores on a chip multiprocessor keeps increasing, Now a days we are increasing the processing level of the chip ,NOC is a best method to interconnect the core with each other core on the chip, In this paper we are creating a network concept on a chip by interconnecting the core with each other core. Then we are reducing the overall chip power and Traffic level by sharing the work load with other cores on the chip, And Dynamic Voltage Frequency Scaling (DVFS) is the technique for monitoring the Frequency/Voltage level of each core on the chip and providing sufficient power to the cores, Application Traffic Prediction Table(ATPT) is a Table that having (low and high) Frequency level table of the Each core. ATPT has very high prediction accuracy. Depends upon the ATPT table voltage/frequency is given to the cores by DVFS. Keyword: Network On Chip, Traffic prediction, Dynamic voltage frequency scaling, Application traffic prediction table Table